Implementation of Multiple Kernels for Edge Detection using Pipelined Architecture on FPGA

Nowadays, image processing plays a vital role in various applications like medical imaging, robotics, and autonomous vehicles. This paper proposes an optimized pipeline architecture for accurate detection of edges by an efficient implementation of multiple kernels on FPGA. The presented pipeline architecture combines the Sobel and Sharpen kernels for detecting edges with low noise. This is designed in such a way to reduce the cost, utilization of resources and time. The simulation is carried out using Xilinx Vivado Design Suite for the target of ZedBoard Zynq Evaluation and Development kit and implemented on the ZYBO Zynq™-7000 Development Board, the results shows that the proposed design is better to earlier implementations in terms of less resource utilization and latency. The presented architecture is capable of detecting edges in real-time and can be used for applications such as image enhancement, motion detection, and object detection, which can be achieved with lesser resources and time savings by concurrent convolution of kernels. This architecture is also scalable and can be easily implemented on other FPGA devices using the Zynq 7000 SoC. The results state the proposed architecture is capable of reducing noise, detects edges in real-time with accuracy, and can be used for real-time applications.