Design and Implementation of Low Power Flash Analog to Digital Converter

The study describes the design and modeling of 3-bit Flash type Analog to Digital converter that is power-efficient. The single inverter type comparator and multiplexer type encoder are used in the design of the FADC. The output of comparator circuit can be either “zero” or “one,” depending on the input voltage used. A single inverter comparator uses 3.799uW of electricity. The encoder using multiplexers transforms thermometer codes into equivalent digital values. The developed encoder circuit has average power consumption of 11.73nW and a latency of 2.51nseconds. Using Cadence analogue design tools in the 180nm process technology library, a 3-bit Flash ADC is created and simulated. At an operating frequency of 10MHz, the proposed design's post layout simulation results reveal average power consumption of 62.9uW and a latency of 2.832ns.