Realization of DTMOS based 6T SRAM cells and their performance analysis at 32nm technology node

The SRAM cells are extensively used in on-chip cache memory in devices such as microprocessors, computers, games controller, and mobile phones etc. This paper examines the performance of six transistor SRAM cell with DTMOS as access/pull-up/pull-down transistors and in combination totaling to seven topologies. Copious simulations in LT spice environment have been performed to compute static and dynamic performance of all the seven topologies using 32 nm PTM model parameters. It is found that pull-up and pull-down based DTMOS structure gives best matrices for stability while access only DTMOS structure gives best delay performance.