A Holistic Approach to System Design Technology Co-Optimization for Deep Single Digit Nodes

The increasing complexity of process technology and demand for computing have led to unsustainable chip costs with marginal performance and power improvement. SDTCO (System Design Technology Co-Optimization) is proposed to address this cost and performance issues. This paper reviews the key SDTCO knobs to improve the PPACt (Power Performance Area Cost and Time-to-market), covering the novel processes and interrelationships between different knobs and key performance indicators in MOL (Middle of Line) and BEOL (Back End of Line) process. Holistic SDTCO evaluation and optimization methods taking from unit process to system level KPI (Key Performance Index) are needed for sustainable cost per transistor scaling and reasonable power and performance improvement.