Neural Network Architectures for Integrated Circuits

This paper presents the architectural design and implementation of neural networks (NNs) for integrated circuit design. The architecture consists of the adder, multiplier, and rectified linear unit (ReLU) blocks. Three architectures (i) single-in single-out (SISO), (ii) multiple-in single-out (MISO), and (iii) multiple-in multiple-out (MIMO) are developed. In NNs, weight values are required, fed from a manually generated memory. The weight values were prepared by training the NNs model on software. Finally, the SISO, MISO, and MIMO neural-networks were taped out.