Design of low-power and high-performance 10 nm SRAM using Electrostatically doped TMD TFET

In this work, a comparison of the Electrostatically Doped Tunnel Field-Effect Transistor (EDTFET) with Transition Metal Dichalcogenide (TMD) as channel material and Si MOSFET-based Static Random Access Memory (SRAM) has been carried out at the circuit level using a Verilog-A interface. A 6T SRAM has been implemented in Cadence Virtuoso for this comparison. It has been observed that the EDTFET SRAM demonstrates superior performance in terms of HOLD, WRITE, and READ noise margins and delay, while maintaining power dissipation at a comparable level. The HOLD, WRITE, and READ noise margins of the EDTFET are 0.2313 V, 0.06 V, and 0.2824 V, respectively, which are 33.93 %, 20 %, and 31.96 % higher than the HOLD, WRITE, and READ noise margins of the Si MOSFET-based SRAM. The delay achieved by the EDTFET-based SRAM is 4 decades lower than that of the Si MOSFET-based SRAM.