Energy Efficient Implementation of Processing Elements for CNN Hardware Accelerator

Deep Learning has been a trending area for researchers in multi-domain applications. Extending its use to platforms with more limited resources, large volumes of data, and energy is a challenge in embedded devices or mobile technology. The objectives to decrease the model size and increase the hardware processing efficiency have led to significantly more compact structural designs for Deep Neural Networks and significant data sparsity. Since convolution in deep learning is the most computationally intensive and time-consuming operation, it is desirable to have specialized hardware with energy-efficient and high throughput features to enhance the throughput factor. This work will take advantage of the hardware parallelism and the sparsity of weights for performance enhancement. In this paper, the system design can provide better hardware acceleration and energy efficiency for fixed-size convolutional neural networks (CNN) processing. The RTL design implementation in System Verilog and the results are analyzed for power for both gate level synthesis in Cadence Genus for 45 nm node with FPGA synthesis using Xilinx Vivado.