Implementation of CMOS Logic Gates Using ASiNR-based TFET

Silicene has drawn wide attention as a promising candidate for potential application in the semiconductor industry because of its two-dimensional structure and the possibility of a band gap opening in a zero-gap material. In this study, we investigate a current transport model in a TFET based on Armchair Silicene Nano-Ribbons (ASiNR). The SiO2 insulating layer between the Si wafer and the silicene channel enables source and drain contact in silicene-based FETs' native Ag pads, which can be defined using a recently developed etch-back technique. The channel length and width are taken as 30 nm and 1.4 nm, respectively. The band gap opening for ASiNR has been determined to be.56 eV for widths less than 2 nm. Based on the results of our transport model research, in the off state, or leakage current at VGS = 0 V, the value is roughly 29 nA/m, which is on par with that of a commercially available silicene-based FET. Similar to the outcome for a silicene-based FET, the ION/IOFF ratio is close to 60 that has been put into actual use. According to the math, the swing below the threshold is 8 mV every decade. Given the device’s modest power consumption, the small magnitude of its subthreshold swing is understandable. MOSFETs have an analogous IDS-VDS characteristic for different VGS.