Two Wilkinson-Power-Combiners designed with Transmission Lines and Lumped Elements in 22 nm FD-SOI CMOS

This paper analyses and compares two sub- 60GHz broadband and low-loss Wilkinson power combiners/dividers (WPCDs) based on transmission lines and lumped elements. Both WPCDs were implemented in a 22nm FDSOI CMOS technology. A two-stage WPCD based on lumped elements was fabricated and compared against the conventional transmission line based WPCD. The lumped element based WPCD enables an area reduction of 33%, while providing similar performance. Both WPCDs show a measured insertion loss (IL) of less than 2.2 dB, a return loss (RL) of better than 10dB and an amplitude and phase error of less than 0.12 dB and 2. 2
^o
from DC up to 65 GHz. The port isolation (ISO) is better than 15 dB from 35 GHz to 60 GHz.