10 GB MAC Core Verification Monitor Module

The research study intends to develop an Object-Oriented Programming (OOP)-based UVM testbench monitor module. According to the OOP model, the testbench is made up of various objects, each of which is intended to perform a specific job of the verification flow. A 10GE MAC Core architecture is being verified. Even though the design comes with a crude test case that provides for some simple logic checks, scaling and/or maintaining such a testbench would be very challenging. This paper aims to provide a clean verification environment output monitor module that is easy to understand, control, and grow due to the tight separation between the RTL domain & the verification domain. This method has demonstrated to be very beneficial when working with the verification of sophisticated digital systems, like those present in today’s applications.