Floating Multiplier based Matrix Multiplication using PPI-MO Technique

DSP systems that are resource efficient, high throughput, and low power are in high demand right now due to the rapid growth of wireless communication, multimedia applications, robotics, and graphics. In almost all DSP systems, from audio/video signal processing to wireless sensor networks, the fundamental processing element that is utilized the most frequently is Floating Point (FP) Matrix Multiplication (MM). The hardware implementation of FP-MM necessitates a large number of arithmetic operations, which have an impact on speed but also take up more space and power. In order to cut down on area, DSP systems use parallel processing and pipelining. MM is the portion activity utilized in many change, picture and discrete sign handling application. New methods and algorithms for MM on configurable devices are developed by us. A proposed three MM design is present in this study. To accommodate various application requirements, these designs reduced input/output data format, throughput rate, and hardware complexity. The PPI-MO based MM is design Xilinx software and simulated number of slice, look up table and delay.