Architectural Radiation Hardening of CMOS Power Management Circuits through Bias Tuning

Within the space electronics industry, several strategies have been implemented to mitigate heavy ion, neutron, and proton induced radiation effects in CMOS processes, including radiation through process technology alterations and through circuit design, layout, and architecture. In this work, a new method is proposed that adaptively calibrates integrated analog circuits in CMOS bulk technology through bias tuning to create a radiation hardened system. In this technique, the device parameters that vary due to total ionizing dose radiation are monitored using built-in-self-test circuitry. These monitored parameters are used to tune and calibrate circuit level performance parameters. This work analyzes the TID radiation induced performance shifts in three critical power management circuits and uses bias tune in each circuit to recover circuit performance. The three circuits include: a ring oscillator, a bandgap voltage reference, and a non-overlap (dead-time) clock generator.