Targeted Custom High-Voltage Stress Patterns on Automotive Designs

Continuous analysis of multiple defective dies on a FinFET design indicated a failure mechanism with resistive defect on one library cell. All the units under study had passed the wafer probe test flow and only failed during internal quality and reliability study flows. In this paper, we present the details of developing and deploying targeted stress and test patterns using custom hand-written User Defined Fault Model (UDFM) files. This was essential to address a failure mechanism that was root-caused to not enough high-voltage stress applied in order to accelerate the resistive defect in wafer probe test flow. The defect location inside this cell created feedback in the circuit that limited the current through the defective path, making it more difficult to both accelerate and detect the existence of the problem in wafer probe test flow. A novel solution using the combination of targeted custom ATPG patterns to stress and accelerate the defect mechanism and custom ATPG patterns to also screen defects were generated using the custom UDFM file and deployed in the wafer probe test flow. Finally, we will present unique silicon fallout data from the targeted custom tests which confirmed effectiveness of targeted stress to accelerate and screen defective die early in wafer probe test flow.