Energy Efficient Memory Decoder for SRAM Based AI Accelerator

Address decoders play a vital role in Static Random-Access Memory (SRAM) memory array architecture to fetch the data in less span of time. As compared to other memory devices, SRAM based Artificial Intelligence (AI) accelerator possess high speed in which memory array address decoder plays a vital role. As a result, the address decoder is the key element for SRAM performance. In this paper, an energy efficient address decoder with low power dissipation is proposed, which can be used for SRAM based AI accelerator. Major part of power consumption of memory chip depends on address decoders. As we go down from higher technology nodes to lower technology nodes, leakage power increases which results in total power consumption. Source biasing technique is used to reduce static power consumption. This paper compares the proposed Address decoder in UMC 65nm technology with existing architectures in terms of power, delay and energy. This decoder design has an improvement of 85.8% average power and 87.46% energy as compared with existing conventional 6-64 decoder circuit using pre-decoding methodology.