SEGR and SEB Analysis of SJVDMOS using SiO2/Si3N4 as Gate Dielectric with Buffer layer

This work presents SJ-VDMOS with buffer and gate stacking of silicon nitride. The proposed engineering (Sio2/Si
3
N
4
gate stack) improves the Si/Sio2 interface Electric field nearly by 42%. In addition, buffer layer in between the epitaxial layer and $\mathrm{N}^{+}$ substrate layer protects the device from the parasitic components during irradiation. The proposed device with both the engineering techniques improves overall pre/post radiation performances. These techniques also show better susceptibility against the SEGR and SEB.