Design and Analysis of 8× 8 SRAM Memory Array using 45 nm Technology at 100 MHz

The main goal of this paper is to build an 8 by 8-bit SRAM memory array using 45nm CMOS technology. The SRAM array is read by a 3-bit address using a 3-to-8 decoder. The SRAM cells are made to operate at 100 MHz Read & Write cycles with the least amount of power usage and the appropriate static noise margin. Through Cadence Virtuoso’s Analog-Design Environment, both the SRAM array and decoder are implemented, tested, and laid out using software models. (ADE).