Implementation of Retiming Technique for Clock Period Optimization by Brute-Force Approach

Recent technology advancements have put a lot of emphasis on the optimization of three main aspects - speed, power, and area. The speed of a digital circuit is always dependent upon clock frequency. The clock frequency of a digital circuit is predominantly influenced by the computational cost of the critical path. The critical path of the digital circuits that contain combinational and sequential elements like FIR, IIR Filters, Multipliers, Adders, Digital Signal Processors (DSPs), etc. can be optimized by rearranging the delay(s) of the critical path, which eventually reduces computational cost without trading with the functionality and input-output relation of the circuit. The term ‘Retiming’ is used to describe the technique of reorganizing the storage elements (registers) in a digital circuit while maintaining its functionality. Currently, python is becoming a choice for a large community of software developers, in the VLSI domain also it is gaining popularity as a scripting language. In this article, the python implementation of the retiming technique is proposed, which takes a Data Flow Graph (DFG) of a non-retimed Digital Circuit as an input to generate the optimized DFG with less critical path delay by Brute Force search, thereby improving overall performance.