Area and Delay Efficient Hybrid Prefix Adders for Residue Number System Applications

The proposed technique uses modified Ling Parallel Prefix adder which reduces logic levels and Kogge-Stone adder which generates carry faster. The Xilinx ISE Design Suite 14.5 is used for verification on Zynq 7000 Series FPGA. The designs are modelled using Verilog HDL and their functionality is verified using ISIM Simulator. It can be seen from comparisons with theoretical and simulated findings that the suggested hybrid adder has less delay than the KoggeStone adder. In addition, the hybrid adder is more space-efficient than the Kogge-Stone adder.