On Generating Cell Library in Advanced Nodes: Efforts and Challenges

With the continuous progress of the manufacturing process, the related design rules become more and more complicated. In order to manufacture high complexity ICs, generating cell library in advanced nodes such as FinFET technology is intriguingly essential for fast circuit layout synthesis. This task was usually in manual process, not to mention in FinFET era. In this work, on top of other FinFET cell library generation works, we propose a methodology, including placement and routing of cells, to generate two cell libraries: ASAP7 PDK and 16nm leading foundry commercial node one. The efforts are presented, as well as the difficulties and challenges we encountered are depicted.