Area Efficient VLSI ASIC Implementation of Multilayer Perceptrons

We propose a simulated annealing (SA) based neural network (NN) optimization approach for designing an area and power efficient hardware model for multilayer perceptrons. Our approach targets optimizing the hidden layer neuron weights to integer values. For each SA move, the subset of the hidden weights is perturbed at random. The perturbation amount (
$p$
) is set proportional to the annealing temperature (
$T$
). All the newly generated weights that are proximate to integers are rounded to the nearest integer to produce an optimized model. To further minimize the hardware, register resizing and operator strength reduction are applied. The objective of preserving the model's accuracy is favored in our approach. Our proposed methodology is validated using five MLP benchmarks. We find the most optimal solution when the temperature reduction rate (
$\alpha$
) is 0.99 and the number of iterations (
$N$
) at each temperature (
$T$
) is 10K. With an average model accuracy degradation of 2.74%, the average savings for the best case scenario for area, power, and FFs are 27.53%, 27.28%, and 27.71%, respectively.