Design and optimization of an on-chip Artificial neural network on FPGA for recognizing handwritten digits

Today's requirement for massive computation power and the inefficiency of deep learning applications are the significant drawbacks holding back the seamless integration of machine learning and deep learning in embedded systems. This paper aims to implement and optimize the neural network for handwritten digit recognition on low-power efficient FPGA devices. The comparative analysis of artificial neural architectures by varying the number of neurons in each layer is performed. This analysis comprises the accuracy of recognition with respect to the resource utilization of FPGAs. MNIST (Modified National Institute of Standards and Technology database) is used to test the neural network. For this implementation, both hardware and software platforms are used. Also, python libraries such as Zynet, TensorFlow, and NumPy are used to train the neural network. Studies have indicated that implementing deep neural networks purely in software can encounter significant constraints in their hardware implementation, specifically in the utilization of critical parameters such as memory, computational resources, and power. Therefore, to tackle these constraints, the Vivado high-level synthesis (Vivado HLS) tool is used, which leverages the advantages of hardware implementation, such as pipelining and parallelism, to improve the performance of FPGAs.