FIVE STAGE PIPELINED MIPS PROCESSOR VERIFICATION SEQUENCE MODULE USING UVM

The MIPS processor layout is one of the very first foundations of the cutting-edge-day processor designs. It brings various fundamental ideas of current-day computing like Pipelining, Data Dependency coping with and forwarding into one location to enhance the abilities and pace of processing. This undertaking proposes to verify the functionality of a five-level pipelined MIPS processor. The design underneath check comes with a complete of 16 instructions with a complete of 49 versions, 5 pipeline tiers and a chance unit. This task offers the verification of this design. The capability of each practice is tested using Constrained Random Verification and the statisticsdependencies being dealt with by the hazard unit are proven byusing Assertion Based Verification. To put into effect those verification strategies in System Verilog Universal Verification Methodology (UVM) is used.