Design of Three-valued Logic Half-Subtractor using GNRFET

The design of three-valued schematics utilizing graphene nanoribbon field effect transistors (GNRFETs) is presented in this paper. Three-valued logic have various benefits over the conventional binary logic such as reduced area, reduced wire complexity, fast-arithmetic and logic operation and large bandwidth. In this work, the standard three-valued inverter (STI), NAND and half subtractor are presented. The proposed schematics are developed using HSPICE for validation. The performances in terms of delay, power and circuit area for GNRFET designs are also evaluated and compared with CNTFET designs. The GNRFET designs show high performance on an average up to 53.2% compared to CNTFET based designs.