Impact of Conduction Current on Output Capacitance Loss in GaN HEMTs

Output capacitance (Coss) loss is generated when the Coss of a power device is charged and discharged, which is ideally a lossless process. This work deploys a recently developed method to measure the Coss loss (EDISS) of GaN power transistors under steady-state switching. This easy-to-implement method allows for the study of EDISS dependences on various parameters, including temperature, dv/dt (or resonant frequency), ON-state current, OFF-state voltage, and steady-state switching frequency. Particular focus is placed on studying the impact of the ON-state current on EDISS, as such impact was either not investigated or coupled with the impact of blocking voltage in prior studies. The EDISS of three mainstream commercial GaN high electron mobility transistors (HEMTs) are comprehensively characterized. We found that all three GaN HEMTs show a linear EDISS increase with the conduction current. These results provide important insights from both the application and device physics standpoints: a) the previously reported EDISS measured with the device constantly OFF may underestimate the EDISS in practical operations; b) the ‘hot’ electron trapping effect tightly correlated with the ON-state current could be a critical origin for the Coss loss in GaN HEMTs.