Conduction performance evaluation of power semiconductor device technologies for solid-state DC breakers

The solid-state DC breakers exhibit high conduction losses due to the high ON-state voltage drop occurring in the power semiconductor devices. This paper presents an experimental evaluation of the ON-state voltage drop of nine commercial
$1200V$
-class power semiconductor device technologies that can be utilized in such breakers. The results revealed the advantageous ON-state performance of the normally-ON SiC JFET at room temperature. In addition, the impact of overdriving the devices by applying the maximum allowable gate voltage on the anticipated conduction losses is also assessed. It is shown that all the investigated devices significantly reduced their ON-state voltage drop under overdrive operation, where the most significant reduction has been observed for normally-ON SiC JFETs. In particular, a 30% reduction of the conduction losses has been achieved at elevated junction temperature when the gate voltage of the normally-ON SiC JFET was increased from OV to 2V.