Low-Power Approximate Adder Architecture for Image Processing Applications

Approximate computing, which is an emerging technology aimed at improving the speed, power, and efficiency where precise computation is not necessary. The paper proposes a new adder architecture that employs an efficient method in the least significant portion. Results demonstrate that the proposed adder architecture achieves better accuracy than existing designs. Specifically, the results show that the proposed architecture can provide up to 37.31% savings in power when compared to existing designs and up to 55.3% improvement in power-delay product. To validate the efficacy of the proposed architecture, image processing applications were used.