Design and analysis of a low power high speed full adder using 2×1 multiplexer

In this research article a novel 1-bit full adder is provided which is implemented by using the 2×1 mux based full adder whose output are improved by a significant amount. Transmission gate are used in the circuit diagram. In this research article an attempt is made to construct 1-bit to 3-bit full adder in 90nm technology. The mux using different full adder have simulated and designed using cadence software in 90nm CMOS technology. Performance parameters are verified by using Monte Carlo and process corner analysis.