Multiplier Design for Digital Modulator for Wireless Communication Applications

State-of-the-art technologies cannot be implemented without being expedited by very large-scale integration (VLSI) circuits because computational complexity is continuously increasing. For example, application-specific integrated circuits (ASICs) are required for 5G communications to attain data rates above tens of gigabits per second. Systems for the Internet of Things (IoT) must have extremely efficient hardware to support data transfer within a few milliseconds while operating within a constrained power budget. The digital design gives greater flexibility than the analog design since the digital communication modules are robust and also provide significant immunity to noise and interference. We have a multichannel technology known as orthogonal frequency division multiplexing (OFDM) that combines QAM and FDM (OFDM). To offer several bit streams with a high data rate, 64-QAM or 256-QAM are employed in separate frequency channels with OFDM in 5G. The proposed design, QAM is built utilizing several multiplier architectures, including Vedic multipliers and booth multipliers, and performance evaluation is done concerning area and power using ASIC and CMOS Technology. Aim of the proposed multipliers is that they require significantly fewer components as compared to the naive method. Further complexity reductions are achieved. The obtained result shows that the use of the multiplier module will outperform state-of-the-art modulator efficiency. Using cadence tool 32bit and 64bit QAM design and physical parameters area and power efficiency are estimated and tabulated respectively.