Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology

To design a high-speed SqRt CSLA(Square Root Carry Select Look Ahead Adder) by using Multiplexer logic in order to reduce the number of gates. Performance comparison of proposed carry select adder with conventional CSLA is performed. SqRt CSLA architectures, including two hybrid designs, a high-speeddesign, and a design with the smallest area in comparison to prior CSLAs is proposed here. The first suggested architecture uses a new, quick add-one and multiplexing circuit to apply an optimized design of the BEC-based CSLA. The available CSLA, needs approximately the equal amount of area but uses significantly less energy and time. In this work a FAM CSLA using Transmission Gates (TG) based Full adder is proposed in 90nm Technology. Simulation results show that the delay of 11.50 ns is obtained which is less when compared with the conventional CSLA architectures.