Edge Zonal Low Yield in FinFET Manufacturing

In FinFET IC manufacturing, we investigated factors causing the low yield at wafer edge. Based on the edge die failure analysis, we visualized structural issues related to the critical processes sensitive to induce in-wafer non-uniformities besides the wafer bevel damages, residues, and flakes. Key processes were identified and various countermeasures were implemented to mitigate issues causing the wafer process non-uniformity across the line, such as in plasma etch, CMP, in addition to proper wafer bevel treatments.