Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications

The requirement for rapid, reliable computing has grown as the semiconductor industry has progressed and the process technology has scaled. The demand for high-processing, low power integrated circuits (ICs) are growing all the time as a result, the need of wireless and wire line communication systems for large data rates have grown to the multi-gigabit per second level. The current study focuses on the design of the PLL system in the Cadence Virtuoso analog design environment tool utilizing the SCL 180nm manufacturing technology (scl pdk 180 nm). A single-ended voltage control oscillator is selected for its superior performance like small chip size, low power consumption, and wide frequency range. In the Cadence Virtuoso tool, the Spectre simulator is used to verify the result of the simulations. The proposed PLL has achieved an output frequency of 7.2 GHz, and power consumption of 3.09 mW. Further jitters, phase noise, and spur are reduced and then compared to the recently reported paper.