Machine Learning Based Flip-Flop Clustering for Clock Network Power Improvement

Power reduction is one of the key challenges in today's SoC implementation. In this work, we have presented an unsupervised Machine Learning based multi-bit flip-flop clustering and relocation framework to address the clock network power reduction without impacting the performance of the design. During clustering of multi-bit flip-flops, localized congestion is experienced. This paper has shown how to mitigate the congestion issue by controlling the cluster size and flop displacement limit. Implementation on external foundry process node shows that our proposed methodology can reduce significant clock wirelength and clock network power, which is leading to 10%, 3%, and 2% reduction in total power respectively in three real industry designs.