Device-Circuit Co-Design and ESD/HCI Reliability Aware Design of Field Plated RF LDMOS Devices

This work explores the scope of Laterally Double Diffused Metal Oxide Semiconductor (LDMOS) for high off-state breakdown voltage with significantly low on-resistance and which can deliver output power above 1000W to the load for the frequency range 27MHz to 3.6GHz. Optimization of field plates (gate field plate and drain field plate) has been done to achieve high breakdown voltage. Further optimization has been done by keeping floating the substrate contact and without sinker of RF LDMOS to achieve more off-state breakdown voltage. The optimization offers 120V off-state breakdown voltage. A model card was generated by using HiSim compact model in IC-CAP industry simulation software to investigate the radio frequency power amplifier performance of FP RF LDMOS designs. The RFPA performance of FP RF LDMOS designs was investigated on Advance Design System simulation software which offered drain efficiency (ηD) of 87%, output power(Pout) more than 60dBm and 25 dBm Gain at 1dB compression point compared to the commercially available NXP device (MRFE6VP61K25H). Electrostatic Discharge (ESD) robustness was studied for the FP RF LDMOS designs as ESD has been identified as a source of damage to unprotected devices. Hot Carrier Injection (HCI) reliability was also investigated to address the complete reliability of these devices.