On the ESD behavior of hydrogenated amorphous silicon based high-voltage TFTs

In this paper, we present detailed physical insights into the electrostatic discharge (ESD) behavior of high-voltage amorphous silicon (a-Si:H) thin-film transistors (TFTs). Device architecture which provides a 4-5x times improvement in ESD robustness with the same spatial considerations is discussed. The physics behind the improvement in ESD robustness is explored, and technological parameters' impact on ESD behavior is studied. Transmission line pulse (TLP) characteristics are discussed, and the failure behavior is explored.