Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation

In FinFETs, the source/drain (S/D) extension regions play a vital role in the device's performance as it modulates the overall parasitic capacitance. Thus, placing a symmetric/asymmetric spacer in the FinFET changes the overall capacitance. This paper demonstrated the impact of putting the symmetric and asymmetric spacer in multi-fin FinFET. We kept the same fin length while changing the source-side and drain-side spacer lengths. The impact of an asymmetric spacer is investigated on the device characteristics, such as ON current, gate capacitance, transconductance, etc., for single and multi-fin configurations. Further, we designed a basic common source (CS) amplifier with resistive load and investigated the circuit level performance using spacer optimization through extensive TCAD simulations. The optimum device performance is observed for asymmetric source and drain spacer length (L
DSP
16nm and L
ssp
= 4nm) for three fins FinFET.