Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress

Physical insights into the impact of the thin-oxide polysilicon gate on the on-resistance of DeMOS-based HV-PNP are developed using detailed TCAD simulation. Turn-on and eventual failure mechanisms in HV-PNP are discussed. The impact of thin-oxide polysilicon placed over the N-Well and P-Well regions is investigated separately. The physics of regenerative bipolar degradation and its effect of dynamic on-resistance is understood as a function of thin-oxide placement. Furthermore, floating the thin-oxide gate mitigated regenerative bipolar degradation while having a faster lateral PNP trigger, resulting in the best case of on-resistance at all current levels. The insights developed in this work help to design compact high-voltage PNPs.

I. Introduction

Automotive applications require stringent qualifications and high current levels under IEC. NPN-based snapback solutions like SCR or HV-NPN can cause non-uniform turn-on-related issues, severely degrading their reliability [1], [2]. HV -PNP solutions are advantageous as they don't suffer any non-uniform turn-on-related problems [3]. However, due to their low failure current and high on-resistance, they usually require a large footprint for protection [3]. Hence optimization of on-resistance is critical for PNP-based protection solutions, as proper on-resistance optimization can significantly reduce the area of protection-cell. Conventionally, the on-resistance of the HV-PNP device is engineered using contact widths or well-profile. Any investigations into the role played by the thin-oxide gate are missing in the literature. This work bridges that gap by developing physical insights into the impact of the thin-oxide gate on the on-resistance of DeMOS-based HV-PNP under ESD stress. It discusses the dynamics of turn-on and eventual failure of a typical HV -PNP device used for ESD protection. Finally, the device in floating gate configuration is investigated based on the physical insights developed in the previous sections to solve the design of a robust PNP-based high voltage protection scheme.