Automatic Origination of Frequency Division Multiplexing in Xilinx-Vivado Environment

This Article demonstrates the implementation of Frequency Division Multiplexing (FDM) by using Verilog Hardware Description Language (VERILOG HDL) in Xilinx software. Our primary objective specifies that in a communication medium, all the signals from different channels are merged and delivered across a single channel. After the transmission to the receiver end, each signal is separated into its specific channel. To execute it we use frequency division multiplexing, which splits the higher bandwidth communication channel’s frequency spectrum into numerous smaller bandwidth communication channels. These channels broadcast signals simultaneously, using various carrier frequencies. To maintain specific channel width between the frequencies, Guard band is required. This concept has been implemented in Xilinx vivado software by using VERILOG HDL. After execution of the main code, inputs to the test bench code are given, for testing purposes. The code is implemented in dataflow method as it specifies that any digital circuit can be implemented in vivado by using VERILOG HDL.