A Highly Stable 10T SRAM Cell for Low Power Applications

Cell stability is a prime concern in today's System-on-a-chip (SoCs) employing nanometer regime transistors. This work presents a read-disturb free 10T SRAM cell which achieves read stability equal to the hold stability. As the proposed cell consists only one bitline for read/write, therefore, lesser switching activities (during read/write) occur leading to low power consumption compared to differential 6T cell. Simulation is done on TSPICE using PTM 90nm CMOS technology. Simulation results show that proposed 10T cell improves read static noise margin (RSNM) by 3.61 x compared to the standard 6T cell at 0.4V. Read (write) power dissipation in the proposed cell is 0.58 x(0.70x) of standard 6T cell. Proposed circuit dissipates 0.66 x lesser static power compared to standard 6T cell. However, due to single-ended writing, write static noise margin (WSNM) is degraded by 0.92x compared to standard 6T cell.