Five Stage Pipelined MIPS Processor Verification Coverage Module Using UVM

The MIPS processor this project intends to verify is a 16bit, 5 staged pipelined processor. It provides sixteen instructions with 49 variants. This verification process of this design involves first verifying individual blocks of each stage and then verifying the overall working of the design. This project presents the verification of this design. The functionality of each instruction is tested using constrained random verification to implement these verification techniques in system Verilog unified verification methodology (UVM) is used. The Coverage of the processor in improved by using the large instruction set and coverage bins are included to check the coverage of each instruction using coverage module.