Efficient FPGA Implementation of Phase Shift Keying

Digital modulation schemes have been an essential part of wireless communication technologies for data transmission. Existing works that implement M-ary PSK using digital logic either have a greater computational complexity due to using arithmetic operations or a more significant area due to using a higher number of LUTs. This paper presents a two look-up table-based modulator capable of generating up to 8-ary PSK at different sampling frequencies with only memory-read operations. From the simulation, it is obtained that the proposed architecture reduces both computational complexity and area without compromising on the characteristics of phase-shift keying.