A Wide-Band High-Speed Sample and Hold in 0.35µm CMOS Technology

The design of a wide-band high-speed Sample and Hold (S&H) is presented herein. A new topology is proposed to address the stringent large bandwidth high-speed requirements of fast data transmissions. In a high-speed communication system, the fast operation of the analog to digital converter (ADC) is required, presenting a great challenge for the S&H design. The main contribution of the proposed design is to minimize the impact of the sampling frequency induced by the switch position. The designed S&H operates with a sampling frequency of 800MHz, an input signal of 80MHz, and a power consumption of 3.05mW. The circuit occupies an area of
$0.0572mm^{2}$
in the
$0.35\mu \mathrm{m}$
CMOS process.