High Security and Low Power AES Crypto Processor Security Algorithm for Image Encryption

Data encryption specifications include the Advanced Encryption Standard (AES) algorithm. This AES algorithm has been incorporated into both hardware and software, making it one of the most used forms of encryption technologies. A symmetric cryptography method with adequate security uses Field Programmable Gate Arrays (FPGA). The proposed design includes 8bit (1-byte) data route and 5 main blocks. The Key Register and State Register are the register banks to store text files, credential keys, and intermediate data. Shift Rows are added to the State Register to reduce an area. The Mix Column will be changed to an 8bit data route. has four internal registers, each of which can send and receive 8 bits, an 8-bit or 1-byte block that is designed for Mix Columns. Additionally, the key expansion and encryption phases employ shared optimized Sub-Bytes. To make different Sub-Bytes more efficient, we combine and streamline them. To cut down on power usage, the design makes use of the clock gating technique. AES architecture for a 128-bit image-based image encryption system is presented in this work. Verilog HDL, Model sim 6.4.c was used to implement this design in an FPGA XC3S 200 TQ-144. To synthesize Xilinx to tool is being used.