CNTFET-based 1-bit Comparator Design using Low-power Logic Circuit Techniques

Carbon nanotube-based FET devices are becoming increasingly popular because of their high channel mobility. In this work, CNTFET-based 1-bit comparator circuits are designed in 32 nm technology using the Complementary CNTFET Technique (CCT) and Pass Transistor Logic (PTL) approaches. The results show Energy Delay Product (EDP) and Power Delay Product (PDP) for the CCT-based 1-bit comparator circuit are $8140\times 10^{-24}$ and 8.1 fJ respectively. While for the PTL-based 1-bit comparator circuit EDP and PDP are $2072\times 10^{-24}$ and 4.1 fJ respectively. These CNTFET-based comparator circuits are likely to be utilized in low-power digital systems on chips