A Comprehensive Cryogenic CMOS Variability and Reliability Assessment using Transistor Arrays

Integrating CMOS circuits and qubits at cryogenic temperatures requires high-frequency operation in the GHz range together with ultra-low power consumption and very low noise figures. One approach to reduce power consumption is to optimize circuits towards operation at lower supply voltages. However, this reduces the tolerable margins on device-to-device variations and parameter degradation. In this study, we present a comprehensive overview on the time-zero performance, variability, and reliability of a 28 nm bulk CMOS technology using thousands of transistors measured from room temperature down to 4 K. Moreover, we present a quantum-mechanical extension of the nonradiative multiphonon (NMP) model derived from bias temperature instability (BTI) measurements on long-channel transistors of the same technology to explain charge trapping kinetics at cryogenic temperatures.