Dual Vt 7T SRAM Based In-Memory Compute Adder for Convolution Neural Network Applications

In artificial Intelligence (AI), frequent movement of data required between memory and computational block. Currently computing platforms suffer from memory wall. Inmemory computing (IMC) provides a solution, by moving memory and processing unit closer. In this article, we present, IMC using dual V
t
7T SRAM+2T cell along with less delay sense amplifier in UMC 65nm technology. To prove its efficiency basic Boolean operations and half adder is implemented. The proposed technique shows an improvement in speed by 43% and 61.95% for carry and sum respectively as compared with already IMC architectures, the early precharge of the sensing delay of sense amplifiers. The proposed half adder has an delay of 0.78ns and an average power dissipation of 36uW.