Modeling of in-plane distortions and overlay errors encountered during 3-D NAND flash device fabrication

A typical 3-D NAND die is segmented into several regions including the scribe lines, peripheral circuit and memory arrays, which are subjected to different processing steps and material combinations, leading to significant variations in mechanical stresses. These give rise to intra-die stress gradients upon wafer clamping, causing significant overlay errors between subsequent processing steps. In this study, we demonstrate a multi-scale finite-element methodology to evaluate the in-plane distortions and expected overlay issues at critical processing steps of 3-D NAND device fabrication. The impacts of pattern densities at the device level and die level are investigated. Using the obtained results, major challenges to characterize overlay patterns are identified and potential solutions are proposed.