A Probability Soft-Error Model for a 28-nm SRAM-based FPGA under Neutron Radiation Exposure

Bit errors due to radiation effects are becoming increasingly important as the fabrication technologies are shrinking with every generation of integrated circuits. The resulting smaller transistors are more prone to high-energy irradiation. This is relevant in avionics or even automotive, where the safety of millions of cars must be ensured. This paper proposes an experiment, where multiple FPGAs (Field Programmable Gate Arrays) are exposed to 2.45MeV neutron irradiation in parallel. Bitflips in different memory components (Block RAM, Flip-Flops, lookup-tables and configuration memory) are detected. The results show that bitflips could be detected in every memory component in every part of the FPGA. Finally, a soft-error probability model depending on the irradiation fluence can be determined. With the probability model, future implementations of fault-tolerant hardware architectures can be tested with hardware simulations using artificially generated bitflips.