Efficient Hardware Implementation of PRESENT Lightweight Cipher

Lightweight block ciphers are preferred for resource-constrained environments to ensure data safety. Two iterative architectures are proposed to achieve efficient hardware implementation of PRESENT cipher with minimized resources. S-box being only nonlinear portion of the algorithm is implemented using Algebraic Normal Form Boolean expression. The number of S-boxes utilized in the design decides the resources required for implementation and the area occupied. The proposed methods are implemented in Spartan and Virtex family FPGA devices. The proposed architecture, with the least S-box occupying 51 Slices in Virtex FPGA and only 1098 GE area in ASIC, exhibits good results and outperformed all the existing work and can be claimed as an optimal choice for resource-constrained environment.