A PRBS Generator and Checker based BIST for Multipliers

Multipliers are commonly used in ASICs and digital signal processors (DSPs). Field Programmable Gate Arrays (FPGAs) are now integrated with embedded modules, memory, DSPs, and logic blocks, requiring efficient Built-in self-tests (BISTs) for complex circuits such as DSP slices. The purpose of BIST is to validate the FPGA's functionality by introducing test patterns and examining the device's response. This paper evaluates the PRBS generator and checker used as a BIST for high data rate transfers in FPGAs. The design achieves less error with logic utilization of less than 2% in available LUT of FPGA. The testing of multipliers present in recent FPGAs is also discussed. Index terms include Built-in Self-test (BIST), Pseudo random binary sequence (PRBS) generator, checker, and BER-Bit Error Rate.