A Survey on Floating Point Arithmetic Units for Non-Linear Application

This paper contributes to the comprehensive study of floating point arithmetic. It lists many researchers’ contributions to improving the general functionality of floating point arithmetic units through the development of numerous new and updated algorithms in a variety of engineering and technological applications. An extensive analysis and presentation of a collection of over 20 research articles and more than 10 survey papers pertaining to various algorithms for various arithmetic units was done to assist future researchers in making meaningful contributions to the field of VLSI. The survey articles considered for this literature are classified into different categories based on performance, accuracy, and area for some specific applications. Because of significant amount of research work has been focused on reducing power consumption during execution, the paper’s comparative study focuses primarily on Performance, takes the parameters into account, and compares them to existing Algorithms. According to the paper that was part of our study, the main goal was to develop various arithmetic units that would keep the overall performance of the floating point arithmetic units balanced over their lifetime while decreasing the area, increasing performance, and requiring less energy for different operations performed by a single arithmetic unit. The work also contributes to the discussion of the difficulties in designing an architecture and algorithm for floating point arithmetic units taking into account the interdependency of different performance criteria. Designing effective floating point architecture is a challenge nowadays because changing floating point architectures is such a challenging subject for researchers.